Zdravím,
obracím se s prosbou ohledně Power-on resetu. Mám MCU PIC18f46K22, na breadboardu mam zapojen jednoduchý obvod, kterým chci otestovat GPIO tohoto MCU - LED a větráček. Zatím se jedná o port A, dva piny mám proudově posíleny unipoláry. Na poli mam stabilizátor LM317, ze kterého mi leze napětí 4.6V, které spínám pomocí těch dvou pinů s tranzistory a tím ovládám svit LED a otáčky větráčku. Samotné MCU napájím pomocí Pickitu3 4.6V a LM317 napájím 24V. O co jde, když chci nahrát jednoduchý testovací prográmek v assembleru do MCU, tak MPLAB X sice udělá build, nahraje ho do MCU, ale MCU nereaguje. Při proměření napětí na pinech PORTU A se chová v podstatě tak, jak je popsáno v datasheetu u Power-on resetu. Poradil by mi někdo, jak se zbavit toho resetu při připojení napájení? Zkoušel jsem zapojení obvodu pro Power-on reset dle datasheetu, ale stav se nezměnil. Rád bych věděl, jak se tomuhle stavu vyhnout, popřípadě jak ho eliminovat na dps při návrhu.
P.s. Blokovací kondenzátory u napájení OZ a MCU používám běžně.
#include "p18f46k22.inc"
; CONFIG1H
CONFIG FOSC = INTIO67 ; Oscillator Selection bits (Internal oscillator block)
CONFIG PLLCFG = OFF ; 4X PLL Enable (Oscillator used directly)
CONFIG PRICLKEN = ON ; Primary clock enable bit (Primary clock is always enabled)
CONFIG FCMEN = OFF ; Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
CONFIG IESO = OFF ; Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
; CONFIG2L
CONFIG PWRTEN = OFF ; Power-up Timer Enable bit (Power up timer disabled)
CONFIG BOREN = OFF ; Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
CONFIG BORV = 190 ; Brown Out Reset Voltage bits (VBOR set to 1.90 V nominal)
; CONFIG2H
CONFIG WDTEN = OFF ; Watchdog Timer Enable bits (Watch dog timer is always disabled. SWDTEN has no effect.)
CONFIG WDTPS = 32768 ; Watchdog Timer Postscale Select bits (1:32768)
; CONFIG3H
CONFIG CCP2MX = PORTC1 ; CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
CONFIG PBADEN = OFF ; PORTB A/D Enable bit (PORTB<5:0> pins are configured as digital I/O on Reset)
CONFIG CCP3MX = PORTB5 ; P3A/CCP3 Mux bit (P3A/CCP3 input/output is multiplexed with RB5)
CONFIG HFOFST = OFF ; HFINTOSC Fast Start-up (HFINTOSC output and ready status are delayed by the oscillator stable status)
CONFIG T3CMX = PORTC0 ; Timer3 Clock input mux bit (T3CKI is on RC0)
CONFIG P2BMX = PORTD2 ; ECCP2 B output mux bit (P2B is on RD2)
CONFIG MCLRE = EXTMCLR ; MCLR Pin Enable bit (MCLR pin enabled, RE3 input pin disabled)
; CONFIG4L
CONFIG STVREN = OFF ; Stack Full/Underflow Reset Enable bit (Stack full/underflow will not cause Reset)
CONFIG LVP = OFF ; Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
CONFIG XINST = OFF ; Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
; CONFIG5L
CONFIG CP0 = OFF ; Code Protection Block 0 (Block 0 (000800-003FFFh) not code-protected)
CONFIG CP1 = OFF ; Code Protection Block 1 (Block 1 (004000-007FFFh) not code-protected)
CONFIG CP2 = OFF ; Code Protection Block 2 (Block 2 (008000-00BFFFh) not code-protected)
CONFIG CP3 = OFF ; Code Protection Block 3 (Block 3 (00C000-00FFFFh) not code-protected)
; CONFIG5H
CONFIG CPB = OFF ; Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
CONFIG CPD = OFF ; Data EEPROM Code Protection bit (Data EEPROM not code-protected)
; CONFIG6L
CONFIG WRT0 = OFF ; Write Protection Block 0 (Block 0 (000800-003FFFh) not write-protected)
CONFIG WRT1 = OFF ; Write Protection Block 1 (Block 1 (004000-007FFFh) not write-protected)
CONFIG WRT2 = OFF ; Write Protection Block 2 (Block 2 (008000-00BFFFh) not write-protected)
CONFIG WRT3 = OFF ; Write Protection Block 3 (Block 3 (00C000-00FFFFh) not write-protected)
; CONFIG6H
CONFIG WRTC = OFF ; Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
CONFIG WRTB = OFF ; Boot Block Write Protection bit (Boot Block (000000-0007FFh) not write-protected)
CONFIG WRTD = OFF ; Data EEPROM Write Protection bit (Data EEPROM not write-protected)
; CONFIG7L
CONFIG EBTR0 = OFF ; Table Read Protection Block 0 (Block 0 (000800-003FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR1 = OFF ; Table Read Protection Block 1 (Block 1 (004000-007FFFh) not protected from table reads executed in other blocks)
CONFIG EBTR2 = OFF ; Table Read Protection Block 2 (Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks)
CONFIG EBTR3 = OFF ; Table Read Protection Block 3 (Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks)
; CONFIG7H
CONFIG EBTRB = OFF ; Boot Block Table Read Protection bit (Boot Block (000000-0007FFh) not protected from table reads executed in other blocks)
RES_VECT CODE 0x0000 ; processor reset vector
GOTO START ; go to beginning of program
; TODO ADD INTERRUPTS HERE IF USED
MAIN_PROG CODE ; let linker place main program
START
movlw 0x3B
movwf OSCCON
movlw 0x87
movwf OSCCON2
movlw 0xC0
movwf PMD0
movlw 0xFF
movwf PMD1
movlw 0x1F
movwf RCON
movlw 0xC
movwf STATUS
movlb 0xF
clrf PORTA
movlw 0x00 ; all pins are digital
movwf ANSELA
movlw 0xF8
movwf TRISA ;RA(0-2) -> output, RA(5-3) -> input
;GOTO $ ; loop forever
END